/**************************************************************************//**
 * @file     pan_phy.c
 * @version  V1.00
 * $Date: 20/12/14 9:39a $
 * @brief    Panchip private rf driver source file
 *
 * @note
 * Copyright (C) 2020 Panchip Technology Corp. All rights reserved.
 *****************************************************************************/
 
#include "PanSeries.h"
#include "pan_phy.h"
#include "pan_pri_rf.h"

#define LOG_ERROR printf
#define PN108C_SOC

const uint32_t init_sleep[] =
{
	0x001900B0
};

const uint32_t pwr_reset[] =
{
	0x0A00E004,
	0x0A03E014  // set pwr_mag_stdbyen & ioring_rst_n
};

const uint32_t phy_init[] =
{
	0x0000ff02,

#ifdef PN108C_SOC
	//modify by yangcheng 20210204
	0x000C7802,
	0x00037902,
	0x00147A02,
#endif
	
#ifndef PN108C_SOC
	0x00506002,
	0x00055c02,
	0x00196302,
#endif
	0x00056202,
	0x00c49002,
	0x00169802,
	0x0000d502,
	0x0020d402,
	0x0005df02,
	0x0057de02,
	0x0014c402,
	0x0009c102,
	0x0078d302,
	
	0x0001bf02,
	0x00027e02,
	0x00a0c202,
	0x00079502,
	0x008a9002,
	
	// RSSI_HYS
	0x0006a202,
	0x0014a302,
	0x0015a302,
	0x0014a302,
	0x0000a302,

	//RSSI_SCALE_FREEZ
	0x00a1a202,
	0x000ea302,
	0x000fa302,
	0x000ea302,
	0x0000a302,

	//RSSI_INIT
	0x00a8a202,
	0x0010a302,
	0x0011a302,
	0x0010a302,
	0x0000a302,
	
	//Rssi_th
	0x00d0a202,  //th1   bb = -69 af = -81  c3 = -61  d0 = -48
	0x0000a302,
	0x0001a302,
	0x0000a302,

//    0x00bba202,  //th2
	0x0002a302,
	0x0003a302,
	0x0002a302,

//    0x00bba202,  //th3
	0x0004a302,
	0x0005a302,
	0x0004a302,
	
//    0x00bba202,  //th4
	0x0006a302,
	0x0007a302,
	0x0006a302,
	
//    0x00bba202,  //th5
	0x0008a302,
	0x0009a302,
	0x0008a302,
	
	0x00c3a202,  //th6
	0x000aa302,
	0x000ba302,
	0x000aa302,
	
	0x00afa202,  //th7
	0x000ca302,
	0x000da302,
	0x000ca302,
	// GAIN WORD
	0x0019a202, //Gain_word0    0x0003a202
	0x0026a302,
	0x0027a302,
	0x0026a302,
	
//    0x0019a202, //Gain_word1    0x0003a202
	0x0028a302,
	0x0029a302,
	0x0028a302,
	
//    0x0019a202, //Gain_word2    0x0003a202
	0x002aa302,
	0x002ba302,
	0x002aa302,
	
//    0x0019a202, //Gain_word3    0x0003a202
	0x002ca302,
	0x002da302,
	0x002ca302,
	
//    0x0019a202, //Gain_word4    0x0003a202
	0x002ea302,
	0x002fa302,
	0x002ea302,
	
//    0x0019a202, //Gain_word5    0x0003a202
	0x0030a302,
	0x0031a302,
	0x0030a302,
	
	0x0016a202, //Gain_word6    0x0003a202
	0x0032a302,
	0x0033a302,
	0x0032a302,
	
	0x001ba202, //Gain_word7    0x001ba202
	0x0034a302,
	0x0035a302,
	0x0034a302,
	
	//CONV
	0x00aca202,
	0x0036a302,
	0x0037a302,
	0x0036a302,
	//FIX
	//fix0
	0x00e9a202,    //0x00dca202
	0x0016a302,
	0x0017a302,
	0x0016a302,
	//fix1
//    0x00e9a202,   //0x00dca202
	0x0018a302,
	0x0019a302,
	0x0018a302,
	//fix2
//    0x00e9a202,   //0x00dca202
	0x001aa302,
	0x001ba302,
	0x001aa302,
	//fix3
//    0x00e9a202,   //0x00dca202
	0x001ca302,
	0x001da302,
	0x001ca302,
	//fix4
//    0x00e9a202,   //0x00dca202
	0x001ea302,
	0x001fa302,
	0x001ea302,
	//fix5
//    0x00e9a202,   //0x00dca202
	0x0020a302,
	0x0021a302,
	0x0020a302,
	//fix6
	0x00dca202,  //0x00dca202
	0x0022a302,
	0x0023a302,
	0x0022a302,
	//fix7
	0x00d6a202,  //0x00c4a202
	0x0024a302,
	0x0025a302,
	0x0024a302,
	0x0000a302,
	//-----------------------  AGC end -------------------------------	
	0x001c2f02,  // modify by yangcheng 20210225  pll bw target  0x001f2f02
	0x00002e02,
	0x00022d02,  //[4:3]=00 16 div  [2:0]=000 jingdu 25khz
	0x00803e02,  //  0x80 er fen fa  0xc0 gongshifa
	//1M  preamble
	//gain
	0x0000da02,  //0x0000da02
	0x0079db02,  //0x005cdb02
	0x0010d902,
	0x0011d902,
	0x0010d902,
	0x0000da02,
	0x0035db02,
	0x0012d902,
	0x0013d902,
	0x0012d902,
	0x00e0da02,
	0x00cfdb02,
	0x0014d902,
	0x0015d902,
	0x0014d902,
	//b1
	0x00c5da02,  //0x00c6da02
	0x0006db02,  //0x0076db02
	0x0016d902,
	0x0017d902,
	0x0016d902,
	0x00e1da02,
	0x00d0db02,
	0x0018d902,
	0x0019d902,
	0x0018d902,
	//b2
	0x001bda02, //0x0019da02
	0x0043db02, //0x00e9db02
	0x001ad902,
	0x001bd902,
	0x001ad902,
	0x00f4da02,
	0x0040db02,
	0x001cd902,
	0x001dd902,
	0x001cd902,

	//2M preamble
	//gain
	0x0005da02,  //0x0001da02
	0x003fdb02,  //0x003fdb02
	0x0020d902,
	0x0021d902,
	0x0020d902,
	0x00ffda02,
	0x00cbdb02,
	0x0022d902,
	0x0023d902,
	0x0022d902,
	0x00e0da02,
	0x007bdb02,
	0x0024d902,
	0x0025d902,
	0x0024d902,
	//b1
	0x00c2da02,  //0x00c2da02
	0x000ddb02,  //0x000cdb02
	0x0026d902,
	0x0027d902,
	0x0026d902,
	0x00e1da02,
	0x0062db02,
	0x0028d902,
	0x0029d902,
	0x0028d902,
	//b2
	0x001eda02,  //0x001eda02
	0x0000db02,  //0x0001db02
	0x002ad902,
	0x002bd902,
	0x002ad902,
	0x00ecda02,
	0x0080db02,
	0x002cd902,
	0x002dd902,
	0x002cd902,


// end

	0x00c25202,  //modify by yangcheng 20210204  0x00c25202
	0x00c05902,  //modify by yangcheng 20210204
	0x00405402,  //modify by yangcheng 20210204

			
	0x0001ff02,
	0x01e20f02,
	0x01400102,
	0x0000ff02,
#ifndef PN108C_SOC
	0x002C6E02,
	0x00855B02,
	0x00855D02,
	0x0A805F02,
	0x05805A02,
#endif
	0x02080202,
	0x64080A02,
	#ifndef USE_OUT_OF_BAND
    0x85080302,  // sig cal  :98    multi-cal 08
    0x00000302,
	#else
    0x85980302,  // sig cal  :98    multi-cal 08 external channel
    0x00900302,
	#endif	
	0x00000A02,
	0x00000202,
	0x02040202,
	0x14080A02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0xFF242D02,
	0x00042D02,
	0x00000A02,
	0x00100202,
	0x00280202,
	0x00014B02,
	0x00232902,
	0x00099502,
	0x001FF502,
	0x0001FF02,
	0x00110002,
	0x00510002,
	0x00710002,
	0x00079E02,
	0x50F10002,
	0x00110002,
	0x00080202,
	0x00009E02,
	0x0000FF02,
	0x00079502,
	0x0000F502,
	0x00004B02,
	0x00202902,
	0x0000FF02,
	0x1E0A0202,
	0xFF204102,
	0x00004102,
	0x00037e02,
	0xFF204102,
	0x00004102,
	0x00027e02,
	0x00040002,
	0x02100202,
	0x1E060a02,
	0x0001FF02,
	0x00110002,
	0xFA910002,
	0x00110002,
	0x0000FF02,
	0x00BFC302,
	0x00697F02,
	0x0001FF02,
	0x00009E02,
	0x28180002,
	0x00100002,
	0x00019E02,
	0x28180002,
	0x00100002,
	0x00029E02,
	0x28180002,
	0x00100002,
	0x00039E02,
	0x28180002,
	0x00100002,
	0x00049E02,
	0x28180002,
	0x00100002,
	0x00059E02,
	0x28180002,
	0x00100002,
	0x00069E02,
	0x28180002,
	0x00100002,
	0x00079E02,
	0x28180002,
	0x00100002,
	0x0000FF02,
	0x00000A02,
	0x00000202,
	0x008FC302,
	
#if 0
	// siyi
	0x000d9502,
	0x001bf502, // 1f 1b 1a 01
#endif

	// 0x00017E02, /* 2M default */

#if 0 // mdm_debug
// mdm_debug start
	0x0001FF02,  // page 2
	0x0036B002,  // P0_01_MFP
	0x0036B102,  // P0_23_MFP
	0x0036B202,  // P0_45_MFP
//    0x0006B302,  // P0_67_MFP
	0x0000FF02,  // page 1
// mdm_debug end
#endif
	
	//added for agc test
	0x00019502,
	0x001ff502,
	0x0023d402,
	0x0001ff02,
	0x00a00302,
	0x0000ff02,
	
	0x00687F12
};



const uint32_t pre_tx_config[] =
{
	0x01027E02,
	0x00A0C202,
	0x0001bf02,
	0x1A080002,
	0x24080a02,
	0x00480002,
#ifdef PN108C_SOC
	0x00947A02,  //modify by yangcheng 20210204
#endif
	0x201c7012
};

const uint32_t pre_tx_config_2M[] =
{
	0x00037E02,
	0x00A0C202,
	0x0001bf02,
	0x1A080002,
	0x26080a02,
	0x00480002,
#ifdef PN108C_SOC
	0x00947A02, // PA, 0dBm
#endif
	0x201c7012
};

const uint32_t pre_tx_config_LR[] =
{
	0x00027E02,
	0x00E0C202,
	0x0001bf02,
	0x1A080002,
	0x26080a02,
	0x00480002,
#ifdef PN108C_SOC
	0x00947A02, // PA, 0dBm
#endif
	0x201c7012
};

const uint32_t post_tx_config[] =
{
	0x1A0c7002,
#ifdef PN108C_SOC
	0x00947A02,  //modify by yangcheng 20210204
#endif
	0x00080012
};

const uint32_t pre_rx_config[] =
{
	//modify by yangcheng 20210205
	0x0A0c7002, //c2:0x0c   c3:0x03
	0x00022802,
	0x00856202,
	0x00206602,
	//end
	
	0x01027E02,
	0x00A0C202,
	0x0001bf02,
	0x00bfc302,
	0x022c0002,
	0x1E060a12
};

const uint32_t pre_rx_config_2M[] =
{
	//modify by yangcheng 20210224
	0x0A0c7002, //c2:0x0c   c3:0x03
	0x00022802,
	0x00004d02,
	0x00856202,
	0x00206602,
	//end
	
	0x01037E02,
	0x00A0C202,
	0x0001bf02,
	0x00bfc302,
	0x022c0002,
	0x1E060a12
};

const uint32_t pre_rx_config_LR[] =
{
	//modify by yangcheng 20210205
	0x0A0c7002, //c2:0x0c   c3:0x03
	0x00022802,
	0x00856202,
	0x00206602,
	//end
	
	0x00027E02,
	0x00E0C202,
	0x0001bf02,
	0x00bfc302,
	0x022c0002,
	0x1E060a12
};

const uint32_t post_rx_config[] =
{
	0x008FC312
};


uint32_t channel_initialize[] =
{
	0x01007D12
};


const uint32_t init_sleep_size                  = sizeof init_sleep;
const uint32_t pwr_reset_size                   = sizeof pwr_reset;
const uint32_t phy_init_size                    = sizeof phy_init;
const uint32_t pre_tx_config_size               = sizeof pre_tx_config;
const uint32_t pre_tx_config_LR_size            = sizeof pre_tx_config_LR;
const uint32_t pre_tx_config_2M_size            = sizeof pre_tx_config_2M;
const uint32_t post_tx_config_size              = sizeof post_tx_config;
const uint32_t pre_rx_config_size               = sizeof pre_rx_config;
const uint32_t pre_rx_config_LR_size            = sizeof pre_rx_config_LR;
const uint32_t pre_rx_config_2M_size            = sizeof pre_rx_config_2M;
const uint32_t post_rx_config_size              = sizeof post_rx_config;
const uint32_t channel_initialize_size          = sizeof channel_initialize;



const uint8_t phy_chan_cfg_reg                    = 0x7D;
const uint8_t phy_rssi_out_reg_adr                = 0x85;


uint8_t phy_set_time_cfg(uint8_t phy, uint8_t tx1rx0)   /*most time is 101us*/
{
	uint8_t ret = 0;
	
	if(phy == 1)  //2m
	{
		if(tx1rx0 == 1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_2M_size>>2);i++)
			{
				ret += ((pre_rx_config_2M[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_2M_size>>2);i++)
			{
				ret += ((pre_tx_config_2M[i] & 0xFF000000) >> 24);
			}
		}
	}
	else  //1m
	{
		if(tx1rx0==1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_size>>2);i++)
			{
				ret += ((pre_rx_config[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_size>>2);i++)
			{
				ret += ((pre_tx_config[i] & 0xFF000000) >> 24);
			}
		}
	}
	return ret;
}

static inline void PHY_FifoFlush(void)
{
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x0);

	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x0);
}

uint32_t PHY_WriteCfgFifoBatch(const uint32_t *command, const uint32_t cmd_len, uint32_t *ptr_rsp_value)
{
	volatile uint32_t reg = 0;
	uint32_t time_out = 0, cmd_idx = 0;
	uint32_t rsp_len = 0;

	if (0 == cmd_len) {
		goto fun_ext;
	}

	/* Flush the PHY Driver FIFO */
	PHY_FifoFlush();

	/* Trigger the FIFO */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x1);

	do {
			do {
					/* check that the FIFO is empty */
					reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FULL);
			} while (reg == 1);

			/* Write the commands to FIFO */
			PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY3, PHY_DRV_CFG_BUF_DIN, command[cmd_idx++]);

			/* check that the Response buff is full */
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);
			if ((ptr_rsp_value != NULL) && (reg == 0)) {
					/* read the response from FIFO */
					ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
			}
	} while (cmd_idx < cmd_len);

	do {
			time_out++;
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, INTR1, IC_PHY_DRV_CFG_DONE);
	} while (reg == 0 && time_out < 255);

	if (time_out == 255)
	{
		goto fun_ext;
	}

	/* check that the Response buff is full */
	reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);

	while ((ptr_rsp_value != NULL) && (reg == 0)) {
			/* read the response from FIFO */
			ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
			/* check that the Response buff is full */
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1,  PHY_DRV_RSP_BUF_EMPTY);
	}

	/* Clear the interrupt */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 0);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x0);

fun_ext:
	return rsp_len;
}

void PHY_reset(void)
{
	/* select PHY scheme */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_REG, 0);
	PHY_WriteCfgFifoBatch(pwr_reset, (pwr_reset_size >> 2), NULL);
}


static inline uint32_t PHY_SeqRamInit(void)
{
	uint32_t j = 0;
	uint32_t seq_ram_index = 0;

	seq_ram_index  = SEQ_RAM_OFST ;
	for (j = 0; j < (post_tx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, post_tx_config[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (post_rx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, post_rx_config[j]);
			seq_ram_index += 4;
	}

	for (j = 0; j < (pre_tx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_tx_config_2M_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_2M[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_tx_config_LR_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_LR[j]);
			seq_ram_index += 4;
	}

	for (j = 0; j < (pre_rx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_rx_config_2M_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_2M[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_rx_config_LR_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_LR[j]);
			seq_ram_index += 4;
	}

	return seq_ram_index;
}

void PHY_SetChConfig(uint8_t chan)
{
	channel_initialize[0] = (channel_initialize[0] & 0xFF00FFFF) | (((0x000000FF & (uint32_t)chan)) << 16);
	PHY_WriteCfgFifoBatch(channel_initialize, (channel_initialize_size >> 2), NULL);
}


void PHY_init(void)
{
	uint32_t tmp;

	if (PHY_SeqRamInit() >= SEQ_RAM_OFST + 512) {
		return;
	}

	tmp = PHY_WriteCfgFifoBatch(phy_init, (phy_init_size >> 2), NULL);
	tmp = PHY_WriteCfgFifoBatch(init_sleep, (init_sleep_size >> 2), NULL);

	/* This field specifies the Sequencer start address for TX end operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_END_ADDR, 0);
	/* This field specifies the Sequencer start address for RX end operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_END_ADDR, (post_tx_config_size >> 2));
	/* Write the address of the RSSI register in the PHY register file so as to the link layer read it
	* and append it to the end of the packet received */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSSI_REG_ADDR, phy_rssi_out_reg_adr);
	/* selecting the new PHY used in Version 5.0 by setting the channel register by 7D*/
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY5, PHY_DRV_SET_CHAN_REG_ADDR, phy_chan_cfg_reg);

#ifdef FPGA_MODE
	// bug fixed (FPGA only): When starting the adv/scan, The ad9364 does not work on the first 37 channel
	PHY_SetChConfig(1);
#endif
}

bool PHY_SetExternChannel(uint16_t rf_channel, uint8_t calibrate)
{
	bool status = true;

	uint32_t cmd_channel[] = {
		0x00805602,
		0x000CB302,
		0x0000B402,
		0x0000B512,
	};

	uint8_t  divider_ratio = 43 + (rf_channel-2400)/32;
	int32_t  tmp           = (rf_channel-2400-(divider_ratio-43)*32)*4096;
	uint32_t offset        = (tmp<0)?(tmp+65536+196608):tmp;

	cmd_channel[0] |= (divider_ratio << 16);
	cmd_channel[1] |= (((offset >> 16) & 0x03) << 16);
	cmd_channel[2] |= (((offset >>  8) & 0xFF) << 16);
	cmd_channel[3] |= (((offset >>  0) & 0xFF) << 16);

	PHY_WriteCfgFifoBatch(cmd_channel, (sizeof cmd_channel >> 2), NULL);

	if (1 == calibrate) {
		PHY_init();
	}

	return status;
}

void PHY_SetTrxSeq(enum tx_rx_phy phy) 
{                
	uint32_t txseq_ram_index = 0;
	uint32_t rxseq_ram_index = 0;

	txseq_ram_index = (post_tx_config_size >> 2)
									+ (post_rx_config_size >> 2);                
	rxseq_ram_index = (post_tx_config_size >> 2)
									+ (post_rx_config_size >> 2)
									+ (pre_tx_config_size >> 2)
									+ (pre_tx_config_2M_size >> 2)
									+ (pre_tx_config_LR_size >> 2);
	
	if (LE_2M == phy)
	{
		txseq_ram_index = txseq_ram_index + (pre_tx_config_size >> 2);
		rxseq_ram_index = rxseq_ram_index + (pre_rx_config_size >> 2);
	}

	/* This field specifies the Sequencer start address for TX start operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_STRT_ADDR, txseq_ram_index);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_END_ADDR, 0);                
	/* This field specifies the Sequencer start address for RX start operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_STRT_ADDR, rxseq_ram_index);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_END_ADDR, 2); 
}

/*** (C) COPYRIGHT 2020 Panchip Technology Corp. ***/
